1. Field of the Invention
The present invention relates to a PLL circuit, a radio terminal device, and a control method of the PLL circuit, and in particular, relates to a PLL circuit that compensates for an offset that arises when a loop gain is switched, a radio terminal device, and a control method of the PLL circuit.
2. Description of the Related Art
A PLL (Phase Locked Loop) circuit is used in a radio communication terminal to lock a carrier frequency to a correct frequency. In recent years, with increasingly finer semiconductor processes, a configuration in which a voltage controlled oscillator (VCO) controlled by an analog voltage is replaced by a digital controlled oscillator (DCO) is increasingly receiving attention.
In a PLL circuit using a VCO in related art, a phase difference between a reference clock and a clock obtained by dividing VCO output is compared using a phase comparator. Here, a circuit that converts a phase difference into pulse widths of three states of up, down, and up+down is used as a general phase comparator and a VCO is controlled by controlling a current source of a charge pump circuit using the pulses and converting the output current into a voltage by a loop filter.
On the other hand, as an example of an ADPLL (All-Digital PLL) circuit using a DCO that is receiving attention in recent years, as shown in FIG. 5 (cited from R. B. Staszewski et al., “All-Digital Phase-Domain TX Frequency Synthesizer for Bluetooth Radios in 0.13 um CMOS, ISSCC2004 Digest”), the DCO is digitally controlled by converting a Fractional component of a time difference corresponding to a phase difference into a digital value by a Time-to-Digital Converter (TDC) circuit and an Integer component into a digital value by an accumulator circuit and giving feedback of these detected digital values corresponding to the phase difference by various methods.